Guide

Intel Celeron M Processor Front Side Bus Design Guidelines
R
74 Intel
®
852GM Chipset Platform Design Guide
Figure 34. Processor and GMCH Host Clock Layout Routing Example
Secondary
Side
GMCH
CPU
FROM
CK - 408
GMCH
BCLK
[
1:0
]
ITP
FLEX
CPU
BCLK[1:0]
ITP
BCLK[1:0]
ITP
Interposer
BCLK[1:0]
GND VIA
Layer3
5.8. Processor GTLREF Layout and Routing
Recommendations
There is one AGTL+ reference voltage pin on the Intel Celeron M Processor, GTLREF, which is used to
set the reference voltage level for the AGTL+ signals (GTLREF). The reference voltage must be
supplied to the GTLREF pin. The voltage level that needs to be supplied to GTLREF must be equal to
2/3 * VCCP ± 2%. The GMCH also requires a reference voltage (MCH_GTLREF) to be supplied to its
HVREF[4:0] pins. The GTLREF voltage divider for both the processor and GMCH cannot be shared.
Thus, both the processor and GMCH must have their own locally generated GTLREF networks. Figure
35 shows the recommended topology for generating GTLREF for the processor using a R1 = 1 kΩ ± 1%
and R2 = 2 kΩ ± 1% resistive divider.