Guide

Platform Design Checklist
R
242 Intel
®
852GM Chipset Platform Design Guide
14.4.2. In Target Probe (ITP)
Pin Name System
Pull-up /Pull-down
Series
Termination
Resistor (
Ω)
Notes
9
BPM[5:0]#
51
Ω pull-up to VCCP
Connect to processor, with resistors placed by the
processor.
DBR#
150-240
Ω pull-up to
V3ALWAYS
If using ITP on interporser card, then DBR#
should also be connected to DBRESET pin at the
processor.
RESET#
51
Ω pull-up to VCCP
If USING ITP700FLEX
150 Ω from pull-
up to
ITP700FLEX
See Notes in Section
14.4.1.
FBO Connect to TCK pin of processor. .
TCK
27.4
Ω ± 1% pull-down
to gnd
Connect to processor, with resistor placed by ITP.
TDI
150
Ω pull-up to VCCP
Connect to processor, with resistor placed by ITP.
TDO
75
Ω pull-up to VCCP
Connect to processor, with resistor placed by ITP.
If ITP not used, this signal can be left as NC.
TMS
39.2
Ω ± 1% pull-up to
VCCP
Connect to processor, with resistor placed by ITP.
TRST#
680
Ω pull-down to gnd
Connect to processor.
VTAP,
VTT[1:0]
Connect to VCCP One 0.1 µF decoupling cap is required.
NOTE: The above recommendation is only for ITP700FLEX. If using other ITP, please refer to the appropriate ITP
documents.
14.4.3. Decoupling Recommendations
Signal Configuration Value Qty Notes
9
VCC[Vcc_core] Connect to VCCP 10 µF 38 X5R/X7R, 1206 package. Use for high
frequency decoupling. Bulk decoupling
will depend on the VR solution. The
maximum Equivalent Series Resistance
should be equal to or less than 2.5 m
Ω.
NOTE: Decoupling guidelines are recommendations based on our reference board design. Customers will need to
take layout and PCB board design into consideration when deciding on overall decoupling solution.