Guide

Platform Clock Routing Guidelines
R
202 Intel
®
852GM Chipset Platform Design Guide
11.2.2. CLK66 Clock Group
The 66-MHz clocks are series terminated and routed point to point on the motherboard, with dedicated
buffers for each of the loads. These clocks are all length tuned to match each other and the CLK33
clocks.
Figure 108. CLK66 Clock Group Topology
L1
Rs
CK408
GMCH
ICH4
L2
Table 81. CLK66 Clock Group Routing Constraints
Parameter Definition
Class Name CLK66
Class Type Individual Nets
Topology Series Terminated Point to Point
Reference Plane Ground Referenced
Single Ended Trace Impedance ( Zo ) 55 Ω ±15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below) 20 mils
Serpentine Spacing 20 mils
Maximum Via Count 4 (per side)
Series Termination Resistor Value 33 Ω ± 5 %
Trace Length Limits – L1 Up to 500 mils (breakout segment)
Trace Length Limits – L2 4.0” to 8.5”
Total Length Range – L1 + L2 4.0” to 9.0”
Length Matching Required Yes (Pin to Pin)
Clock to Clock Length Matching ± 100 mils
CLK66 to CLK66
Breakout Region Exceptions.
(Reduced spacing for GMCH & ICH breakout region)
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
NOTE: The overall length of CLK66 is considered the reference length for all other clocks, except USBCLK and
CLK14. The length of this clock should be set within the range and then used as the basis for defining the
length of all other length matched clocks.