Guide

I/O Subsystem
R
Intel
®
852GM Chipset Platform Design Guide 159
Figure 76. ICH4-M AC’97 – Codec Connection
ICH4-M
Primary
Codec
SYNC
BIT_CLK
SDATA_OUT
AC / MC / AMC
RESET#
SDATA_IN0
Secondary
Codec
SDATA_IN1
AC / MC / AMC
Tertiary
Codec
AC / MC / AMC
SDATA_IN2
Note: If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs
residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the
Intel
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M)I/O Controller Datasheet.
Clocking is provided from the primary codec on the link via AC_BIT_CLK and is derived from a
24.576-MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator
requirements. AC_BIT_CLK is a 12.288-MHz clock driven by the primary codec to the digital
controller (ICH4-M) and to any other codec present. That clock is used as the time base for latching and
driving data.
Clocking AC_BIT_CLK directly off the CK-408 clock chip’s 14.31818 MHz output is
not supported.
The ICH4-M supports wake-on-ring from S1M-S5 via the AC’97 link. The codec asserts AC_SDIN to
wake the system. To provide wake capability and/or caller ID, standby power must be provided to the
modem codec.
The ICH4-M has weak pull-down and pull-ups that are always enabled. This will keep the link from
floating when the AC-link is off or there are no codecs present.
If the Shut-off bit is not set, it implies that there is a codec on the link. Therefore, AC_BIT_CLK and
AC_SDOUT will be driven by the codec and the ICH4-M respectively. However, AC_SDIN0,
AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that
there is at least one codec.