Guide

System Memory Design Guidelines (DDR-SDRAM)
R
108 Intel
®
852GM Chipset Platform Design Guide
7.3.6.2. Command Topology 1 Routing Guidelines
Table 41. Command Topology 1 Routing Guidelines
Parameter Routing Guidelines
Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology Daisy Chain with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55 Ω ± 15%
Nominal Trace Width
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio 2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1
500 mils ± 250 mils
(See Table 44 for exact package lengths.)
Trace Length L1 – GMCH Command Signal Ball to First
SO-DIMM Pad
Min = 0.5 inch
Max = 4.0 inches
Trace Length L2 – First SO-DIMM Pad to Series Resistor
Pad
Max = 1.5 inches
Trace Length L3 – Series Resistor Pad to Second SO-
DIMM Pad
Max = 1.5 inches
Trace Length L2 + L3 – Total SO-DIMM to SO-DIMM
spacing
Max = 3.0 inches
Trace Length L4 – Second SO-DIMM Pad to Parallel
Resistor Pad
Max = 1.0 inches
Series Termination Resistor (Rs) 10 Ω ± 5%
Parallel Termination Resistor (Rt) 56 Ω ± 5%
Maximum Recommended Motherboard Via Count Per
Signal
6
Length Matching Requirements
CMD to SCK/SCK# [5:0]
See length matching Section
7.3.6.3 and Figure 54 for details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4. It is possible to route using four vias if one via is shared that connects to the SO-DIMM1 pad and parallel
termination resistor.