Intel Pentium M Processor Specification Update

Errata
Specification Update Classification 33
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y56. SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment
Selector” to SS and CS Registers
Problem: According to the processor specification, attempting to load a null segment selector
into the CS and SS segment registers should generate a General Protection Fault
(#GP). Although loading a null segment selector to the other segment registers is
allowed, the processor will generate an exception when the segment register holding a
null selector is used to access memory. However, the SYSENTER instruction can
implicitly load a null value to the SS segment selector. This can occur if the value in
SYSENTER_CS_MSR is between FFF8h and FFFBh when the SYSENTER instruction is
executed. This behavior is part of the SYSENTER/SYSEXIT instruction definition; the
content of the SYSTEM_CS_MSR is always incremented by 8 before it is loaded into
the SS. This operation will set the null bit in the segment selector if a null result is
generated, but it does not generate a #GP on the SYSENTER instruction itself. An
exception will be generated as expected when the SS register is used to access
memory, however. The SYSEXIT instruction will also exhibit this behavior for both CS
and SS when executed with the value in SYSENTER_CS_MSR between FFF0h and
FFF3h, or between FFE8h and FFEBh, inclusive.
Implication: These instructions are intended for operating system use. If this erratum occurs (and
the OS does not ensure that the processor never has a null segment selector in the SS
or CS segment registers), the processor’s behavior may become unpredictable,
possibly resulting in system failure.
Workaround: Do not initialize the SYSTEM_CS_MSR with the values between FFF8h and FFFBh,
FFF0h and FFF3h, or FFE8h and FFEBh before executing SYSENTER or SYSEXIT.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y57. The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8)
of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the
following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.