Intel Pentium M Processor Specification Update
Errata
24 Classification Specification Update
Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event
may cause unexpected behavior. The SMC event occurs on a full address match of
code contained in L1 cache.
Implication: Due to this erratum, any of the following events may occur:
1. A data access break point may be incorrectly reported on the instruction pointer
(IP) just before the store instruction.
2. A non-cacheable store can appear twice on the external bus (the first time it will
write only 8 bytes, the second time it will write the entire 16 bytes).
Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y28. Removed; See Erratum Y4
Y29. Removed; See Erratum Y5
Y30. Removed; See Erratum Y6
Y31. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is
UC, the consolidated memory type may be treated as UC (rather than WC as specified
in IA-32 Intel
®
Architecture Software Developer's Manual).
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y32. Under Certain Conditions LTR (Load Task Register) Instruction May
Result in System Hang
Problem: An LTR instruction may result in a system hang if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data. When this
erratum occurs, the memory page may be as UC (rather than WC). This may have a
negative performance impact.