Intel Pentium M Processor Specification Update

Y15. RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault
Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific
Registers) based on the index number placed in ECX. The processor should reject
access to any reserved or unimplemented MSRs by generating #GP(0). However,
there are some invalid MSR addressers for which the processor will not generate
#GP(0). This erratum has not been observed with commercially available software.
Implication: For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined
processor behavior may result.
Workaround: Do not use invalid MSR addresses with RDMSR or WRMSR.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y16. FP Tag Word Corruption
Problem: In some rare cases, fault information generated as the result of instruction execution
may be incorrect. The result is an incorrect FP stack entry.
Implication: This erratum may result in corruption of the FP Tag Word in a way that a non-valid
entry in the FP Stack may become valid. The software is not expected to read a non-
valid entry. If the software attempts to use the stack entry (which is expected to be
empty) the result may be an erroneous “Stack overflow”.
Workaround: Do not disable SSE/SSE2 in control register CR4 and avoid Code Segment Limit
violation.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y17. Unable to Disable Reads/Writes to Performance Monitoring Related
MSRs
Problem: The Performance Monitoring Available bit in the Miscellaneous Processor Features MSR
(IA32_MISC_ENABLES.7) was defined so that when it is cleared to a 0,
RDMSR/WRMSR/RDPMC instructions would return all zeros for reads of and prevent
any writes to Performance Monitoring related MSRs. Currently it is possible to read
from or write to Performance Monitoring related MSRs when the Performance
Monitoring Available bit is cleared to a 0.
Implication: It is not possible to disallow reads and writes to the Performance Monitoring MSRs.
Intel has not observed this erratum with any commercially available software or
system.
Workaround: None.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y18. Move to Control Register Instruction May Generate a Breakpoint
Report
Problem: A move (MOV) to Control Register (CR) instruction where Control Register is CR0, CR3
or CR4 may generate a breakpoint report.