Intel Pentium M Processor Specification Update

Errata
Specification Update 17
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y5. FST Instruction with Numeric and Null Segment Exceptions May
Cause General Protection Faults to Be Missed and FP Linear Address
(FLA) Mismatch
Problem: FST instruction combined with numeric and null segment exceptions may cause
General Protection Faults to be missed and FP Linear Address (FLA) mismatch.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: None.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y6. Code Segment (CS) Is Wrong on SMM Handler When SMBASE Is Not
Aligned
Problem: With SMBASE being relocated to a non-aligned address, during SMM entry the CS can
be improperly updated which can lead to an incorrect SMM handler.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Align SMBASE to 32 KB.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y7. A Locked Data Access that Spans Across Two Pages May Cause the
System to Hang
Problem: An instruction with lock data access that spans across two pages may, given some
rare internal conditions, hang the system.
Implication: When this erratum occurs, the system may hang. Intel has not observed this erratum
with any commercially available software or system.
Workaround: A locked data access should always be aligned.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y8. Processor Can Enter a Livelock Condition under Certain Conditions
When FP Exception Is Pending
Problem: Processor clock modulation may be controlled via a processor register
(IA32_THERM_CONTROL) or via the STPCLK# signal. While the Processor clock is
constantly being actively modulated at 12.5% and 25% duty cycles and there is a
pending unmasked FP exception (ES pending), if you attempt a FP load (or MMX™