Intel Pentium M Processor Specification Update

Summary Tables of Changes
12 Specification Update
Stepping
NO.
B1
Plans ERRATA
Y37 X NoFix
Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May
Cause General Protection (#GP) Exception if the Reserved Bits are Set
to One
Y38 X No Fix INIT does not clear global entries in the TLB
Y39 X NoFix
Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang or a Machine Check Exception
Y40 X NoFix
Machine Check Exception May Occur When Interleaving Code between
Different Memory Types
Y41 X NoFix
Split I/O Writes Adjacent to Retry of APIC End of Interrupt (EOI)
Request May Cause Livelock Condition
Y42 X No Fix
General Protection (#GP) Fault May Not Be Signaled On Data Segment
Limit Violation above 4-G Limit
Y43 X No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Y44 X No Fix
Processor INIT# Will Cause a System Hang if Triggered During an NMI
Interrupt Routine Performed During Shutdown
Y45 X No Fix
Certain Performance Monitoring Counters Related to Bus, L2 Cache and
Power Management are Inaccurate
Y46 X No Fix
CS Limit Violation on RSM May be Serviced before Higher Priority
Interrupts/Exceptions
Y47 X No Fix
A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Y48 X No Fix The Processor May Report a #TS Instead of a #GP Fault
Y49 X No Fix
Writing the Local Vector Table (LVT) when an interrupt is pending may cause an
unexpected interrupt
Y50 X No Fix
Using 2M/4M Pages When A20M# is Asserted May Result in Incorrect Address
Translations
Y51 X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
Y52 X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads
to Partial Memory Update
Y53 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Y54 X No Fix FP Inexact-Result Exception Flag May Not Be Set
Y55 X No Fix MOV To/From Debug Registers Causes Debug Exception
Y56 X No Fix
SYSENTER/SYSEXIT Instructions Can Implicitly Load “Null Segment Selector”
to SS and CS Registers
Y57 X No Fix The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
Y58 X No Fix Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
Y59 X No Fix Unaligned Accesses to Paging Structures May Cause the Processor to Hang