Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
32 Specification Update
be incorrect. Note: This issue would only occur when one of the 3 above mentioned
debug support facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X45. The BS Flag in DR6 May Be Set for Non-Single-Step #DB Exception
Problem: DR6 BS (Single Step, bit 14) flag may be incorrectly set when the TF (Trap Flag, bit 8)
of the EFLAGS Register is set, and a #DB (Debug Exception) occurs due to one of the
following:
• DR7 GD (General Detect, bit 13) being bit set;
• INT1 instruction;
• Code breakpoint
Implication: The BS flag may be incorrectly set for non-single-step #DB exception.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X46. BTM/BTS Branch-From Instruction Address May Be Incorrect for
Software Interrupts
Problem: When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software
interrupt may result in the overwriting of BTM/BTS branch-from instruction address by
the LBR (Last Branch Record) branch-from instruction address.
Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X47. Fault on ENTER Instruction May Result in Unexpected Values on Stack
Frame
Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum,
if execution of the ENTER instruction results in a fault, the dynamic storage area of the
resultant stack frame may contain unexpected values (i.e. residual stack data as a
result of processing the fault).
Implication: Data in the created stack frame may be altered following a fault on the ENTER
instruction. Please refer to "Procedure Calls For Block-Structured Languages" in the
IA-32 Intel
®
Architecture Software Developer’s Manual, Vol. 1, Basic Architecture, for
information on the usage of the ENTER instructions. This erratum is not expected to
occur in ring 3. Faults are usually processed in ring 0 and stack switch occurs when
transferring to ring 0. Intel has not observed this erratum on any commercially-
available software.