Intel Pentium M Processor Datasheet

8 Intel
®
Pentium
®
M Processor Datasheet
Introduction
• Micro-op Fusion and Advanced Stack Management that reduce the number of micro-ops
handled by the processor.
• Advanced branch prediction architecture that significantly reduces the number of mispredicted
branches.
• Double-precision floating-point instructions enhance performance for applications that require
greater range and precision, including scientific and engineering applications and advanced 3D
geometry techniques, such as ray tracing.
Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel
products.
The Intel Pentium M processor is offered in two packages: a socketable Micro Flip-Chip Pin Grid
Array (Micro-FCPGA) and a surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA)
package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero
insertion force (ZIF) socket, which is referred to as the mPGA479M socket.
1.1 Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
“System Bus” refers to the interface between the processor and system core logic (also known as
the chipset components).