Guide

Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines
R
Intel
®
852GM Chipset Platform Design Guide 45
Figure 16. Routing Illustration for Topology 3
CPU ICH4-M
L2
L3
L1
Rs
3.3V
3904
3904
FWH
L4
3.3V
Q1
Q2
R1
R2
V_IO_FWH
Table 11. Layout Recommendations for Topology 3
L1 + L2 L3 L4 Rs R1 R2 Transmission Line
Type
0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 300 Ω ± 5% 2kΩ ± 5% 300 Ω ± 5% Micro-strip
0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 300 Ω ± 5% 2kΩ ± 5% 300 Ω ± 5% Strip-line
Figure 17. Voltage Translation Circuit for 3.3-V Receivers
1.3K ohm
+/- 5%
330 ohm
+/- 5%
3.3V
To Receive
r
From Drive
r
3904
3904
Q1
Q2
3.3V
Rs
R1
R2
330 ohm
+/- 5%
4.4. ITP Debug Port
Please refer to the ITP700 Debug Port Design Guide, which can be found on
http://developer.intel.com/design/Xeon/guides/249679.htm
.
Note: This change is effective for all future processors and includes information on both ITP700 and ITP700
Flex.