Guide

System Overview

Intel

852GM Chipset Platform Design Guide 25

• 3D Graphics Engine

⎯ 3D Setup and Render Engine

⎯ High quality performance Texture Engine

• Analog Display Support

⎯ 350-MHz integrated 24-bit RAMDAC

⎯ Hardware color cursor support

⎯ Accompanying I2C and DDC channels provided through multiplexed interface

⎯ Hotplug and display support

⎯ Dual independent pipe for dual independent display

• Digital Video Out Port (DVO) support

⎯ Single channel DVO Port with 165-MHz dot clock support for a 12-bit interface

⎯ Compliant with DVI Specification 1.0

• Dedicated LFP (local flat panel) interface

⎯ Single or dual channel LVDS TFT panel support up to SXGA+ panel resolution with

frequency range from 25 MHz to 112 MHz per channel

⎯ SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock

⎯ Dual Display Twin (Single pipe LVDS+CRT) is not supported if SSC is enabled

⎯ Supports data format of 18 bpp

⎯ LCD panel power sequencing compliant with SPWG timing specification

⎯ Compliant with ANSI/TIA/EIA –644-1995 spec

⎯ Integrated PWM interface for LCD backlight inverter control

⎯ Compliant with CPIS Specification 1.5

⎯ Bi-linear Panel fitting

2.3.2.1. Packaging/Power

• 732-pin Micro-FCBGA (37.5 mm x 37.5 mm)

• VTTLF, VTTHF (1.05 V);

• VCC, VCCASM, VCCHL, VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB (1.2 V);

• VCCADAC, VCCDVO, VCCDLVDS, VCCALVDS, (1.5 V);

• VCCSM, VCCQSM, VCCTXLVDS (2.5 V);

• VCCGPIO (3.3 V)

2.3.3. I/O Controller Hub (ICH4-M)

The ICH4-M provides the I/O subsystem with access to the rest of the system:

• Upstream Accelerated Hub Architecture interface for access to the GMCH

• PCI 2.2 interface (6 PCI Request/Grant Pairs)

• Bus Master IDE controller (supports Ultra ATA 100/66/33)

• USB 1.1 and USB 2.0 Host Controllers

• High Speed Debug port via USB interface

• SMBus 2.0 Controller