Intel Pentium M Processor Specification Update

Errata
26 Classification Specification Update
Workaround: User mode code should not count on being able to recover from illegal accesses to
memory regions protected with supervisor only access when using FP instructions.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y36. Snoops during the Execution of a HLT (Halt) Instruction May Lead to
Unpredictable System Behavior
Problem: If during the execution of a HLT instruction an external snoop causes an eviction from
the instruction fetch unit (IFU) instruction cache, the processor may, on exit from the
HLT state, erroneously read stale data from the victim cache.
Implication: This erratum may lead to unpredictable system behavior. Intel has only observed this
condition in non-mobile configurations.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y37. Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May
Cause General Protection (#GP) Exception If the Reserved Bits Are
Set to One
Problem: Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the
reserved bits set to one may cause a General Protection (#GP) exception.
Implication: Intel has not observed this erratum with any commercially available software.
Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y38. INIT Does Not Clear Global Entries in the TLB
Problem: INIT may not flush a TLB entry when:
1. The processor is in protected mode with paging enabled and the page global
enable flag is set (PGE bit of CR4 register)
2. G bit for the page table entry is set
3. TLB entry is present in TLB when INIT occurs
Implication: Software may encounter unexpected page fault or incorrect address translation due to
a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)
registers before writing to memory early in BIOS code to clear all the global entries
from TLB.
Status: For the steppings affected, see the Summary of Tables of Changes
.