Intel Pentium M Processor Specification Update

Errata
Specification Update 19
Y12. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after
MOV SS/POP SS Instruction if it is Followed by an Instruction That
Signals a Floating Point Exception
Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints
until after execution of the following instruction. This is intended to allow the
sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without
having an invalid stack during interrupt handling. However, an enabled debug
breakpoint or single step trap may be taken after MOV SS/POP SS if this instruction is
followed by an instruction that signals a floating point exception rather than a MOV
[r/e]SP, [r/e]BP instruction. This results in a debug exception being signaled on an
unexpected instruction boundary since the MOV SS/POP SS and the following
instruction should be executed atomically.
Implication: This can result in incorrect signaling of a debug exception and possibly a mismatched
Stack Segment and Stack Pointer. If MOV SS/POP SS is not followed by a MOV
[r/e]SP, [r/e]BP, there may be a mismatched Stack Segment and Stack Pointer on
any exception. Intel has not observed this erratum with any commercially available
software, or system.
Workaround: As recommended in the IA32 Intel
®
Architecture Software Developer’s Manual, the
use of MOV SS/POP SS in conjunction with MOV [r/e]SP, [r/e]BP will avoid the failure
since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception.
Developers of debug tools should be aware of the potential incorrect debug event
signaling created by this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y13. SysEnter and SysExit Instructions May Write Incorrect Requestor
Privilege Level (RPL) in the FP Code Segment Selector (FCS)
Problem: SysEnter and SysExit instructions may write incorrect RPL in the FP Code Segment
selector (FCS). As a result of this, the RPL field in FCS may be corrupted.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y14. Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Problem: This erratum has not been observed with commercially available software.
Implication: This erratum has not been observed with commercially available software.
Workaround: Software that needs to implement memory aliasing in this way should manage the
consistency of the Accessed and Dirty bits.
Status: For the steppings affected, see the Summary of Tables of Changes
.