Intel Pentium M Processor Datasheet

66 Intel
®
Pentium
®
M Processor Datasheet
Package Mechanical Specifications and Pin Information
PRDY# Output
Probe Ready signal used by debug tools to determine processor debug
readiness.
Please refer to the
ITP700 Debug Port Design Guide and the platform design
guides for more implementation details.
PREQ# Input
Probe Request signal used by debug tools to request debug operation of the
processor.
Please refer to the
ITP700 Debug Port Design Guide and the platform design
guides for more implementation details.
PROCHOT# Output
PROCHOT# (Processor Hot) will go active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
has been activated, if enabled. See Chapter 5 for more details.
For termination requirements please refer to the platform design guides.
This signal may require voltage translation on the motherboard. Please refer to
the platform design guides for more details.
PSI# Output
Processor Power Status Indicator signal. This signal is asserted when the
processor is in a lower state (Deep Sleep and Deeper Sleep). See Section 2.1.3
for more details.
PWRGOOD Input
PWRGOOD (Power Good) is a processor input. The processor requires this
signal as a clean indication that the clocks and power supplies are stable and
within their specifications. ‘Clean’ implies that the signal will remain low (capable
of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven inactive at
any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout the boundary scan operation.
For termination requirements please refer to the platform design guides.
REQ[4:0]#
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins of both
processor system bus agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB[0]#.
RESET# Input
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least two milliseconds after
V
CC and BCLK have reached their proper specifications. On observing active
RESET#, both system bus agents will deassert their outputs within two clocks.
All processor straps must be valid within the specified setup time before
RESET# is deasserted.
Please refer to the
ITP700 Debug Port Design Guide and the platform design
guides for termination requirements and implementation details. There is a 55
ohm (nominal) on die pullup resistor on this signal.
RS[2:0]# Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of both processor system bus agents.
RSVD
Reserved/
No
Connect
These pins are RESERVED and must be left unconnected on the board.
However, it is recommended that routing channels to these pins on the board be
kept open for possible future use. Please refer to the platform design guides for
more details.
Table 22. Signal Description (Sheet 5 of 7)
Name Type Description