Guide

Platform Clock Routing Guidelines
R
200 Intel
®
852GM Chipset Platform Design Guide
Table 79. Host Clock Group Routing Constraints
Parameter Definition
Class Name HCLK
Class Type Individual Differential Pairs
Topology Differential Source Shunt Terminated
Reference Plane Ground Referenced (contiguous over length)
Single Ended Trace Impedance ( Zo ) 55 Ω ± 15%
Differential Mode Impedance (Zdiff) 100 Ω ± 15%
Nominal Inner Layer Trace Width 4.0 mils
Nominal Inner Layer Pair Spacing (edge to
edge)(except as allowed below)
7.0 mils
Nominal Outer Layer Trace Width 5.0 mils (pin escapes only)
Nominal Outer Layer Pair Spacing (edge to edge) 5.0 mils
Minimum Spacing to Other Signals 25 mils
Serpentine Spacing 25 mils
Maximum Via Count 5 (per side)
Series Termination Resistor Value 33 ohms ± 5%
Shunt Termination Resistor Value 49.9 ohms ± 1%
Trace Length Limits – L1 & L1’ Up to 500mils
Trace Length Limits – L2 & L2’ Up to 200 mils
Trace Length Limits – L3 & L3’ Up to 500 mils
Trace Length Limits – L4 & L4’ 2.0” to 8.0”
Total Length Range– L1 + L2 + L4 2.0” to 8.5”
Length Matching Required Yes (Package Compensated Pin to Pad)
HCLK to HCLKlk# Length Matching ± 10 mils (per segment)
± 10 mils (overall)
CPU Clock to GMCH Clock Length Matching Match HCLKs (pin to pad) ± 20 mils
Match L1 segment to ± 10 mils across all pairs.
(See Section
11.2.1.2.)
Breakout Region Exceptions No breakout exceptions allowed.
Clock to Clock Skew Budget
(Measured at receiver crossing point)
250 ps (interconnect only)
400 ps (total skew, including 150 ps driver skew)
NOTES:
1. Differential pairs should be routed as a closely coupled side-by-side pair on a single layer over their entire
length.
2. To minimize skew, Intel recommends that all clocks be routed on a single layer. If clock pairs are to be routed
on multiple layers, the routed length on each layer should be equalized across all clock pairs.
3. To minimize skew, Intel recommends that all clock pairs be length matched from CK408 pin to CPU and GMCH
die-pad, and length compensated on the motherboard for differences in package length and for
socket/interposer effective length. A table of package lengths and equivalent socket length is provided.
4. The motherboard length of the ITP connector clock pair should be matched to the motherboard length of the
CPU clock pair.