Intel Pentium M Processor Specification Update

Errata
Specification Update Classification 25
Implication: This erratum may result in system hang if all conditions have been met. This erratum
has not been observed in commercial operating systems or software. For performance
reasons, GDT is typically aligned to 8-bytes.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y33. Loading from Memory Type USWC (Uncacheable Speculative Write
Combine) May Get Its Data Internally Forwarded from a Previous
Pending Store
Problem: A load from memory type USWC may get its data internally forwarded from a pending
store. As a result, the expected load may never be issued to the external bus.
Implication: When this erratum occurs, a USWC load request may be satisfied without being
observed on the external bus. There are no known usage models where this behavior
results in any negative side-effects.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y34. FPU Operand Pointer May Not be Cleared Following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87
FPU Operand (Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector
(both fields form the FPUDataPointer). Saving the floating point environment with
FSTENV, FNSTENV, or floating point state with FSAVE, FNSAVE or FXSAVE before an
intervening FP instruction may save uninitialized values for the FPUDataPointer.
Implication: When this erratum occurs, the values for FPUDataPointer in the saved floating point
image or floating point environment structure may appear to be random values.
Executing any non-control FP instruction with memory operand will initialize the
FPUDataPointer. Intel has not observed this erratum with any commercially available
software.
Workaround: After initialization, do not expect the FPUDataPointer in a floating point state or
floating point environment saved memory image to be correct, until at least one non-
control FP instruction with a memory operand has been executed.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y35. FSTP (Floating Point Store) Instruction under Certain Conditions May
Result In Erroneously Setting a Valid Bit on an FP (Floating Point)
Stack Register
Problem: An FSTP instruction with a PDE/PTE (Page Directory Entry/Page Table Entry) A/D bit
update followed by user mode access fault due to a code fetch to a page that has
supervisor only access permission may result in erroneously setting a valid bit of an
FP stack register. The FP top of stack pointer is unchanged.
Implication: This erratum may cause an unexpected stack overflow.