Intel Pentium M Processor Specification Update

Errata
32 Classification Specification Update
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not
be used.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y54. FP Inexact-Result Exception Flag May Not Be Set
Problem: Problem: When the result of a floating-point operation is not exactly representable
in the destination format (1/3 in binary form, for example), an inexact-result
(precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status
word) is normally set by the processor. Under certain rare conditions, this bit may not
be set when this rounding occurs. However, other actions taken by the processor
(invoking the software exception handler if the exception is unmasked) are not
affected. This erratum can only occur if the floating-point operation which causes the
precision exception is immediately followed by one of the following instructions:
• FST m32real
• FST m64real
• FSTP m32real
• FSTP m64real
• FSTP m80real|
• FIST m16int
• FIST m32int
• FISTP m16int|
• FISTP m32int
• FISTP m64int
Note that even if this combination of instructions is encountered, there is also a
dependency on the internal pipelining and execution state of both instructions in the
processor.
Implication: Inexact-result exceptions are commonly masked or ignored by applications, as it
happens frequently, and produces a rounded result acceptable to most applications.
The PE bit of the FPU status word may not always be set upon receiving an inexact-
result exception. Thus, if these exceptions are unmasked, a floating-point error
exception handler may not recognize that a precision exception occurred. Note that
this is a “sticky” bit, i.e., once set by an inexact-result condition, it remains set until
cleared by software.
Workaround: This condition can be avoided by inserting two non-floating-point instructions between
the two floating-point instructions.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y55. MOV To/From Debug Registers Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from debug register, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.