Intel Pentium M Processor Specification Update

Errata
Specification Update Classification 31
Y51. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: If any of the below circumstances occur it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
1) If an instruction that performs a memory load causes a code segment limit
violation
2) If a waiting floating-point instruction or MMX instruction that performs a memory
load has a floating-point exception pending
3) If an MMX or SSE instruction that performs a memory load and has either
CR0.EM=1 (Emulation bit set), or a floating-point Top-of-Stack (FP TOS) not equal to
0, or a DNA exception pending
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, nor from the
restart and subsequent re-execution of that instruction by the exception handler. If
the target of the load is to uncached memory that has a system side-effect, restarting
the instruction may cause unexpected system behavior due to the repetition of the
side-effect.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y52. Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround: Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y53. Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering
their data invalid. The corresponding data if sent out as a BTM on the system bus will
also be incorrect.
Note: This issue would only occur when one of the 3 above mentioned debug support
facilities are used.