Intel Pentium M Processor Specification Update

Errata
28 Classification Specification Update
Implication: A processor livelock may occur causing a system hang. This issue has only been
observed in synthetic lab testing conditions and has not been seen in any
commercially available applications. The erratum does not occur with Intel mobile
chipset-based platforms.
Workaround: Use the PIC instead of the APIC for the interrupt controller.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y42. General Protection (#GP) Fault May Not Be Signaled On Data
Segment Limit Violation above 4-G Limit
Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4-G
limit (0ffffffffh) may not signal a #GP fault.
Implication: When such memory accesses occur, the system may not issue a #GP fault.
Workaround: Software should ensure that memory accesses do not occur above the 4-G limit
(0ffffffffh).
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y43. DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Retired (Event CFH)
Problem: Performance monitoring for Event CFH normally increments on saturating SIMD
instruction retired. Regardless of DR7 programming, if the linear address of a retiring
memory store MOVD/MOVQ/MOVNTQ instruction executed matches the address in
DR3, the CFH counter may be incorrectly incremented.
Implication: The value observed for performance monitoring count for saturating SIMD instructions
retired may be too high. The size of the error is dependent on the number of
occurrences of the conditions described above, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y44. Processor INIT# Will Cause a System Hang if Triggered during an
NMI Interrupt Routine Performed during Shutdown
Problem: During the execution of an NMI interrupt handler, if shutdown occurs followed by the
INIT# signal being triggered, the processor will attempt initialization but fail soft
reset.
Implication: Due to this erratum, the system may hang.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes
.