Intel Pentium M Processor Specification Update

Y39. Use of Memory Aliasing with Inconsistent Memory Type May Cause
System Hang or a Machine Check Exception
Problem: Software that implements memory aliasing by having more than one linear addresses
mapped to the same physical page with different cache types may cause the system
to hang or to report a machine check exception (MCE). This would occur if one of the
addresses is non-cacheable and used in a code segment and the other is a cacheable
address. If the cacheable address finds its way into the instruction cache, and the
non-cacheable address is fetched in the IFU, the processor may invalidate the non-
cacheable address from the fetch unit. Any micro-architectural event that causes
instruction restart will be expecting this instruction to still be in the fetch unit and lack
of it will cause a system hang or an MCE.
Implication: This erratum has not been observed with commercially available software.
Workaround: Although it is possible to have a single physical page mapped by two different linear
addresses with different memory types, Intel has strongly discouraged this practice as
it may lead to undefined results. Software that needs to implement memory aliasing
should manage the memory type consistency.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y40. Machine Check Exception May Occur When Interleaving Code
between Different Memory Types
Problem: A small window of opportunity exists where code fetches interleaved between different
memory types may cause a machine check exception. A complex set of micro-
architectural boundary conditions is required to expose this window.
Implication: Interleaved instruction fetches between different memory types may result in a
machine check exception. The system may hang if machine check exceptions are
disabled. Intel has not observed the occurrence of this erratum while running
commercially available applications or operating systems.
Workaround: Software can avoid this erratum by placing a serializing instruction between code
fetches between different memory types.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y41. Split I/O Writes Adjacent to Retry of APIC End of Interrupt (EOI)
Request May Cause Livelock Condition
Problem: When Split I/O instruction writes occur adjacent to a retry of a Local APIC End of
Interrupt (EOI) request by the chipset, a livelock condition may result. The required
sequences of events are:
4. The processor issues a Local APIC EOI message.
5. The chipset responds with a retry because its downstream ports are full. It
expects the processor to return with the same EOI request.
6. The processor issues a Split I/O write instruction instead.
7. The chipset responds with a retry because it expected the APIC EOI.
8. The processor insists the Split I/O write instruction must be completed and issues
write instruction again.