Intel Pentium M Processor Specification Update

Errata
22 Classification Specification Update
multiple speculative branches and memory accesses, there exists a one cycle long
window in which the processor may signal a MCE in the Instruction Fetch Unit (IFU)
because instructions previously decoded have been evicted from the IFU. The one
cycle long window is opened when an opportunistic fetch receives a partial hit on a
previously executed but not as yet completed store resident in the store buffer. The
resulting partial hit erroneously causes the eviction of a line from the IFU at a time
when the processor is expecting the line to still be present. If the MCE for this
particular IFU event is disabled, execution will continue normally.
Implication: While this erratum may occur on a system with any number of processors, the
probability of occurrence increases with the number of processors. If this erratum
does occur, a machine check exception will result. Note systems that implement an
operating system that does not enable the Machine Check Architecture will be
completely unaffected by this erratum (e.g., Windows* 95 and Windows 98).
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y22. POPF and POPFD Instructions That Set the Trap Flag Bit May Cause
Unpredictable Processor Behavior
Problem: In some rare cases, POPF and POPFD instructions that set the Trap Flag (TF) bit in the
EFLAGS register (causing the processor to enter Single-Step mode) may cause
unpredictable processor behavior.
Implication: Single-Step operation is typically enabled during software debug activities, not during
normal system operation.
Workaround: There is no workaround for Single-Step operation in commercially available software.
For debug activities on custom software the POPF and POPFD instructions could be
immediately followed by a NOP instruction to facilitate correct execution.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y23. Performance Event Counter Returns Incorrect Value on L2_LINES_IN
Event
Problem: The performance event counter returns an incorrect value on L2_LINES_IN event
(EMON event #24H) when the L2 cache is disabled.
Implication: Due to this erratum, L2_LINES_IN performance event counter should not be
monitored while the L2 cache is disabled. This erratum has no functional impact.
Workaround: Ignore L2_LINES_IN event when the L2 cache is disabled.
Status: For the steppings affected, see the Summary of Tables of Changes
.
Y24. VM Bit Will Be Cleared on a Double Fault Handler
Problem: Following a task switch to a Double Fault Handler that was initiated while the
processor was in virtual-8086 (VM86) mode, the VM bit will be incorrectly cleared in
EFLAGS.