Intel Pentium M Processor Specification Update

Summary Tables of Changes
Specification Update 11
Stepping
NO.
B1
Plans ERRATA
Y14 X NoFix
Memory Aliasing with Inconsistent A and D Bits May Cause Processor
Deadlock
Y15 X NoFix RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault
Y16 X NoFix FP Tag Word Corruption
Y17 X NoFix
Unable to Disable Reads/Writes to Performance Monitoring Related
MSRs
Y18 X NoFix Move to Control Register Instruction May Generate a Breakpoint Report
Y19 X NoFix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations
Y20 X NoFix
The FXSAVE, STOS, or MOVS Instruction May Cause a Store Ordering
Violation When Data Crosses a Page with a UC Memory Type
Y21 X NoFix
Machine Check Exception May Occur Due to Improper Line Eviction in
the IFU
Y22 X NoFix
POPF and POPFD Instructions That Set the Trap Flag Bit May Cause
Unpredictable Processor Behavior
Y23 X NoFix
Performance Event Counter Returns Incorrect Value on L2_LINES_IN
Event
Y24 X NoFix VM Bit Will Be Cleared on a Double Fault Handler
Y25 X NoFix
Code Fetch Matching Disabled Debug Register May Cause Debug
Exception
Y26 X NoFix Upper Four PAT Entries Not Usable with Mode B or Mode C Paging
Y27 X NoFix
SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC)
Event May Cause Unexpected Behavior
Y28 Removed, see Erratum Y4
Y29 Removed, see Erratum Y5
Y30 Removed, see Erratum Y6
Y31 X NoFix
Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) Is UC (Uncacheable) May Consolidate to UC
Y32 X NoFix
Under Certain Conditions LTR (Load Task Register) Instruction May
Result in System Hang
Y33 X NoFix
Loading from Memory Type USWC (Uncacheable Speculative Write
Combine) May Get Its Data Internally Forwarded from a Previous
Pending Store
Y34 X NoFix FPU Operand Pointer May Not be Cleared Following FINIT/FNINIT
Y35 X NoFix
FSTP (Floating Point Store) Instruction Under Certain Conditions May
Result In Erroneously Setting a Valid Bit on an FP (Floating Point)
Stack Register
Y36 X NoFix
Snoops during the Execution of a HLT (Halt) Instruction May Lead to
Unpredictable System Behavior