Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
28 Specification Update
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X32. CS Limit Violation on RSM May Be Serviced before Higher Priority
Interrupts/Exceptions
Problem: When the processor encounters a CS (Code Segment) limit violation, a #GP (General
Protection Exception) fault is generated after all higher priority Interrupts and
exceptions are serviced. Because of this erratum, if RSM (Resume from System
Management Mode) returns to execution flow where a CS limit violation occurs, the
#GP fault may be serviced before a higher priority Interrupt or Exception (e.g. NMI
(Non-Maskable Interrupt), Debug break(#DB), Machine Check (#MC), etc.).
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X33. A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
Problem: With respect to the retirement of instructions, stores to the uncacheable memory-
based APIC register space are handled in a non-synchronized way. For example if an
instruction that masks the interrupt flag, e.g. CLI, is executed soon after an
uncacheable write to the Task Priority Register (TPR) that lowers the APIC priority, the
interrupt masking operation may take effect before the actual priority has been
lowered. This may cause interrupts whose priority is lower than the initial TPR, but
higher than the final TPR, to not be serviced until the interrupt enabled flag is finally
set, i.e. by STI instruction. Interrupts will remain pending and are not lost.
Implication: In this example the processor may allow interrupts to be accepted but may delay their
service.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X34. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X35. BTS Message May Be Lost When the STPCLK# Signal Is Active