Specification Update

R
Intel
®
E7205 Chipset MCH
Specification Update 7
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification Clarifications or
Documentation Changes, which apply to the listed Intel
®
E7205 chipset MCH steppings. Intel intends to
fix some of the errata in a future stepping of the component, and to account for the other outstanding
issues through documentation or Specification Changes as noted. This table uses the following notations:
Codes Used in Summary Table
X: Erratum, Specification Change or Clarification that applies to this stepping.
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification change does not
apply to listed stepping.
Shaded: This item is either new or modified from the previous version of the
document.
Number B0 Plans ERRATA
E1 X NoFix tVAL(min) Timing Is Not Meeting AGP 3.0 Specification
E2 X NoFix AGP Prefetch Cache Must Be Disabled
Number SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision.
Number SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision.
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.