Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Errata
Specification Update 23
Workaround: None identified.
Status: For the steppings affected, see the Summary of Tables of Changes.
X15. Under Certain Conditions LTR (Load Task Register) Instruction May
Result in System Hang
Problem: An LTR instruction may result in a system hang if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data.
Implication: This erratum may result in system hang if all conditions have been met. This erratum
has not been observed in commercial operating systems or software. For
performance reasons, GDT is typically aligned to 8-bytes.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary of Tables of Changes.
X16. Loading from Memory Type USWC (Uncacheable Speculative Write
Combine) May Get Its Data Internally Forwarded from a Previous
Pending Store
Problem: A load from memory type USWC may get its data internally forwarded from a pending
store. As a result, the expected load may never be issued to the external bus.
Implication: When this erratum occurs, a USWC load request may be satisfied without being
observed on the external bus. There are no known usage models where this behavior
results in any negative side-effects.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary of Tables of Changes.
X17. FXSAVE after FNINIT without an Intervening FP (Floating Point)
Instruction May Save Uninitialized Values for FDP (x87 FPU
Instruction Operand (Data) Pointer Offset) and FDS (x87 FPU
Instruction Operand (Data) Pointer Selector)
Problem: An FXSAVE after FNINIT without an intervening FP instruction may save uninitialized
values for FDP and FDS.
Implication: When this erratum occurs, the values for FDP/FDS in the FXSAVE structure may
appear to be random values. These values will be initialized by the first FP instruction
executed after the FXRSTOR that restore the saved floating point state. Any FP
instruction with memory operand will initialize FDP/FDS. Intel has not observed this
erratum with any commercially available software.
Workaround: After an FINIT, do not expect the FXSAVE memory image to be correct, until at least
one FP instruction with a memory operand has been executed.