Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update

Summary Tables of Changes
Specification Update 11
NO.
B1
C0
Plans
ERRATA
X13
Removed, see Erratum X1.
X14
X
X
No Fix
Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) is UC (Uncacheable) May Consolidate to UC
X15
X
X
No Fix
Under Certain Conditions LTR (Load Task Register) Instruction May
Result in System Hang
X16
X
X
No Fix
Loading from Memory Type USWC (Uncacheable Speculative Write
Combine) May Get Its Data Internally Forwarded from a Previous
Pending Store
X17
X
X
No Fix
FXSAVE after FNINIT without an Intervening FP (Floating Point)
Instruction May Save Uninitialized Values for FDP (x87 FPU
Instruction Operand (Data) Pointer Offset) and FDS (x87 FPU
Instruction Operand (Data) Pointer Selector)
X18
X
X
No Fix
FSTP (Floating Point Store) Instruction under Certain Conditions May
Result In Erroneously Setting a Valid Bit on an FP (Floating Point)
Stack Register
X19
X
No Fix
An Execute Disable Bit Violation May Occur on a Data Page-Fault
X20
X
No Fix
CPUID Leaf 0x80000006 May Provide the Incorrect Value for an 8-
Way Associative Cache
X21
X
PlanFix
Snoops during the Execution of a HLT (Halt) Instruction May Lead to
Unexpected System Behavior
X22
X
X
No Fix
Invalid Entries in Page-Directory-Pointer-Table-Register (PDPTR) May
Cause General Protection (#GP) Exception if the Reserved Bits are
Set to One
X23
X
X
No Fix
INIT Does Not Clear Global Entries in the TLB
X24
X
X
No Fix
Use of Memory Aliasing with Inconsistent Memory Type May Cause a
System Hang or a Machine Check Exception
X25
X
X
No Fix
Machine Check Exception May Occur When Interleaving Code
between Different Memory Types
X26
X
X
No Fix
Split I/O Writes Adjacent to Retry of APIC End of Interrupt (EOI)
Request May Cause Livelock Condition
X27
X
X
No Fix
General Protection (#GP) Fault May Not Be Signaled On Data
Segment Limit Violation above 4G Limit
X28
X
X
No Fix
DR3 Address Match on MOVD/MOVQ/MOVNTQ Memory Store
Instruction May Incorrectly Increment Performance Monitoring Count
for Saturating SIMD Instructions Executed (Event B1h)
X29
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced
before Higher Priority Interrupts
X30
X
X
No Fix
Processor INIT# Will Cause a System Hang If Triggered during an
NMI Interrupt Routine Performed during Shutdown
X31
X
X
No Fix
Certain Performance Monitoring Counters Related to Bus, L2 Cache
and Power Management Are Inaccurate
X32
X
X
No Fix
CS Limit Violation on RSM May Be Serviced before Higher Priority
Interrupts/Exceptions