Guide

System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
852GM Chipset Platform Design Guide 85
7.3. Topologies and Routing Guidelines
The Intel 852GM GMCH chipset’s Double Data Rate (DDR) SDRAM system memory interface
implements the low swing, high-speed, terminated SSTL_2 topology. This section contains information
related to the recommended interconnect topologies and routing guidelines for each of the signal groups
that comprise the DDR interface. When implemented as defined, these guidelines will provide a robust
DDR solution on an Intel 852GM GMCH chipset based design.
7.3.1. Clock Signals – SCK[4,3,1,0], SCK#[4,3,1,0]
The clock signal group includes the differential clock pairs SCK/SCK#[4,3,1,0]. The GMCH generates
and drives these differential clock signals required by the DDR interface; therefore, no external clock
driver is required for the DDR interface. The GMCH only supports unbuffered DDR SO-DIMMs; three
differential clock pairs are routed to each SO-DIMM connector. Table 32 summarizes the clock signal
mapping.
Table 32. Clock Signal Mapping
Signal Relative To
SCK/SCK#[1:0] SO-DIMM0
SCK/SCK#[4:3] SO-DIMM1
7.3.2. Clock Topology Diagram
The Intel 852GM GMCH provides six differential clock output pairs, or three clock pairs per SO-DIMM
socket. The motherboard clock routing topology is shown below for reference. Refer to the routing
guidelines in Table 2 on the follow page for detailed length and spacing rules for each segment. The
clock signals should be routed as closely coupled differential pairs over the entire length. Spacing to
other DDR signals should not be less than 20 mils. Isolation spacing to non-DDR signals should be 25
mils.
Figure 43. DDR Clock Routing Topology SCK/SCK#[5:0]
P1
L1
SO-DIMM PADS
Differential Pairs
GMCH
P1
L2
R1
GMCH
Pin
L1 L2
The clock signals should be routed as closely coupled differential pairs over the entire length. Spacing
to other DDR signals should not be less than 20 mils. Isolation spacing to non-DDR signals should be
25 mils.