Guide

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout:
R4G2 needs to be
placed w/in 1" of
divider circuit
Layout:
C5C1 needs 20 mil trace no
more than 1/2" from pin14
Intel 852GM GMCH VR Controller
C26116 4.403
Intel 852GM GMCH VR and VCCP
B
43 51Wednesday, January 12, 2005
Intel Celeron M / 852GM CRB
Title
Size Document Number Rev
Date: Sheet
of
Project:
6225_BST1
6225_OC2
6225_BOOT26225_BOOT1
6225_LG1
6225_SS1
6225_OC1
6225_SS2
6225_VSEN2
VDC_VTTVR +VDC_MCHVR
6225_BST2
Vcc-mch_PWRGD
Vccp_PWRGD
+V5S_VTTMCH
6225_SNUB2
6225_SNUB1
6225_ISEN2
6225_VOUT1
6225_VSEN1
6225_UG1 6225_UG2
6225_LG2
6225_PH26225_PH1
VR_ON 32,37VR_ON32,37
+V5S
5
..18,20,23..25,27,34,35,38..41,45,46
+VDC 16,21,39,41,45
+V3.3S
3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38..40,45,51
+VDC 16,21,39,41,45
+VCCP
3..5,9,18..20,40,42,46
+V1.35S_GMCH
9,46
CORE_VR_ON 39
VOUT_EVMC_B3946
1.35V_EV
46
R5N11 0
CR5C1
BAT54WT1
13
C6C5
0.15UF
C5C1
1uF
R5P10 2K_1%
R5P4
100K_1%
R6C5 .002 5%
C6C8
10UF
U5C2
ISL6225
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
VOUT1
VSEN1
OCSET1
SOFT1
DDR
VIN PG1
PG2/REF
SOFT2
OCSET2
VSEN2
VOUT2
EN2
ISEN2
BOOT2
UGATE2
PHASE2
PGND2
LGATE2
VCC
R5P5
1.69K
1%
C6C2
0.01UF
R5P6
10K_1%
Q5C2A
SI4966DY
2
1
78
R5C3
NO_STUFF_0
R5P11
2K_1%
R5P1
10K
R6C3 .002
5%
C6C1
0.1UF
C6C3
0.01UF
R6P2
43.2_1%
R5C2 0
R6P3
3.32K
1%
U5C1
74AHC1G08
1
2
4
53
Q5C2B
SI4966DY
4
3
56
R6P1
100K_1%
R5P7
6.65K
1%
TP6C1
NO_STUFF_102276-100
L5C1
4.7uH
1 2
Q5C1A
SI4966DY
2
1
7 8
TP5C1
NO_STUFF_102276-100
R5P2
10K
L5C2
4.7uH
1 2
C5C6
10UF
C5C2
0.01UF
C5C5
4.7UF
C5P1
NO_STUFF_1000PF
R6C11
NO_STUFF_0
Q5C1B
SI4966DY
4
3
5 6
R5P9
66.5
1%
CR6C1
BAT54WT1
13
C5C3
0.01UF
C6P1
NO_STUFF_1000PF
C5C4
0.15UF
R6C8 0
R5C1 .002 5%