Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 81
Datasheet Volume One, February 2014
Electrical Specifications
since this is the path to the system BIOS. See Table 6-9 for a list of output tri-state
FRB signals.
Socket level FRB will tri-state processor outputs via the PROCHOT_N signal. Assertion
of the PROCHOT_N signal through RESET_N de-assertion will tri-state processor
outputs. Note, that individual core disabling is also supported for those cases where
disabling the entire package is not desired.
The Intel® Xeon® E7v2 processor extends the FRB capability to the core granularity by
maintaining a register in the uncore so that BIOS or another entity can disable one or
more specific processor cores.
6.5 Mixing Processors
Intel supports and validates two and four processor configurations only in which all
processors operate with the same Intel QuickPath Interconnect frequency, core
frequency, power segment, and have the same internal cache sizes. Mixing components
operating at different internal clock frequencies is not supported and will not be
validated by Intel. Combining processors from different power segments is also not
supported.
Note: Processors within a system must operate at the same frequency per bits [15:8] of the
FLEX_RATIO MSR (Address: 194h); however this does not apply to frequency
transitions initiated due to thermal events, Extended HALT, Enhanced Intel SpeedStep
Technology transitions signal.
Table 6-8. Fault Resilient Booting (Output Tri-State) Signals
Output Tri-State Signal Groups Signals
Intel QPI QPI0_CLKTX_DN[1:0]
QPI0_CLKTX_DP[1:0]
QPI0_DTX_DN[19:00]
QPI0_DTX_DP[19:00]
QPI1_CLKTX_DN[1:0]
QPI1_CLKTX_DP[1:0]
QPI1_DTX_DN[19:00]
QPI1_DTX_DP[19:00]
SMBus MEM_SCL_C[3:0]
MEM_SDA_C[3:0]
VPP_SCL
VPP_SDA
JTAG & TAP TDO
Processor Sideband CAT_ERR_N
CPU_ONLY_RESET
ERROR_N[2:0]
MEM_HOT_C01_N
MEM_HOT_C23_N
BPM_N[7:0]
PRDY_N
THERMTRIP_N
PROCHOT_N
PECI
TSC_SYNC
SVID SVIDCLK
SVID_DATA
SVID_IDLE_N