Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 101
Datasheet Volume One, February 2014
Electrical Specifications
Figure 6-16. SMBus Timing Waveform
Figure 6-17. BCLK to JTAG/TAP Signals Output Valid Delay
Figure 6-18. JTAG/TAP Output Valid Delay Timing Waveform
Data
Clk
P P
SS
STOP STOPSTART START
t
LOW
t
R
t
HD;STA
t
HD;DAT
t
BUF
HIGH
t
t
SU;DAT
t
t
SU;STA
t
HD;STA
SU;STO
t
F
V = 0.5 * V
TT
BCLK
Signal
T
5
Data Valid
V
V = 0.5 * V
TT
TCK
Signal
Ts
V
Th
Data Valid