Hub Datasheet

58 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.5.17 DRB—DRAM Row Boundary Register (D0:F0)
Address Offset: 60–67h (DRB[0:7])
Default Value: 00h
Attribute: RO
Size: 8 bits x 8 registers
The DRAM Row Boundary registers defines the upper boundary address of each DRAM row with
a granularity of 64 MB. Each row has its own single-byte DRB register. For example, a value of 1
in DRB0 indicates that 64 MB of DRAM has been populated in the first row. In this mode a row
spans across both DIMMs.
Bits
Default,
Access
Description
7:0
00h
R/W
DRAM Row Boundary Address. This 8-bit value defines the upper address for each of
the DRAM rows. This 8-bit value is compared against a set of address lines to determine
the upper address limit of a particular row. This field corresponds to bits 33:26 of the
address. A DRAM row is addressed if the address is below the row’s DRAM Row
Boundary Address and greater than or equal to the previous row’s DRAM Row
Boundary Address.
Figure 3-2. Memory Socket Rows Description
DIMM PAIR
Even Row (or Single Sided) Odd row (Present if Double-Sided)
Row Number Address of DRB Row Number Address of DRB
DIMM 1 Row 0 60h Row 1 61h
DIMM 2 Row 2 62h Row 3 63h
DIMM 3 Row 4 64h Row 5 65h
DIMM 4 Row 6 66h Row 7 67h
6 Memory Rows
0 / 1 2 / 3 4 / 5
Slots 0, 2, 4
Channel A
Slots 1, 3, 5
Channel B
72 bit memory socket or slot contain half of
2 different 144 bit rows
- Double sided DIMMs exist in multiple rows
Slot 0/1 contain memory for DRB
0/1 and are closest to the MCH
DIMM pairs - 2 matching DIMMs
sharing rows
- One DIMM in channel A and one in
channel B
Each 144 bit memory row stretches
across 2 memory sockets or slots
- Half of a row is in channel A, half of
a row is in channel B
0 2 4
1 3 5