Hub Datasheet
162 Intel
®
E7505 Chipset MCH Datasheet
Functional Description
5.4.7 AGP Aperture and GART
The MCH contains the AGP aperture and GART capabilities to allow address translation of AGP
accesses. This capability is very similar to previous chipsets.
The AGP aperture may be anywhere from 4 MB to 256 MB in size in binary increments The
default is 256 MB. It is placed above the top of low memory by the PCI plug-and-play software.
The GART address is always naturally aligned to its size, as is required by PCI plug-and-play.
The MCH supports 4-K page sizes. Optional larger sizes of the AGP Specification 3.0 are not
supported.
A memory location must not be accessed through the aperture by one stream or master, and directly
via its memory address by another stream or master. Coherency issues may result. Address
0000_0000h must not be allocated to AGP memory.
5.4.8 Peer-to-Peer Traffic
Peer writes from any hub interface to AGP are permitted. These will appear as PCI semantic write
cycles to the AGP device and may appear as fast writes. Reads from any hub interface to AGP are
not permitted. Neither reads nor writes from a PCI master are permitted to a hub interface.
5.4.9 AGP Electrical Characteristics
The MCH supports AGP 3.0 and AGP 2.0 signaling. The selected mode is determined by the
voltage applied to the PREF_AGP[1:0] pins. It is set during RESET and can not change
dynamically.
AGP 3.0 signaling uses 0.8 V levels. It is selected by PREF_AGP[1:0] being at 0.35 V. The VDDQ
I/O supply voltage is nominally 1.5 V, allowing it to be common to AGP 3.0 or AGP 2.0 signaling.
AGP 3.0 signaling uses a 50 Ω termination to ground on each end when not driving the interface,
so the idle state of the signals is low. Most command and control signals are inverted in AGP 3.0
signaling compared to AGP 2.0 signaling; the control signal inversions minimizes static current
flow during idle bus conditions.
AGP 2.0 signaling uses the full 1.5 V rail-to-rail swing. It is selected by PREF_AGP[1:0] being at
0.75 V during RESET.
The AGP connector has two pins to determine the signaling mode. This flexibility allows both the
motherboards and graphics cards to support both modes.
Table 5-5. Data Rates and Signaling Levels Supported by the MCH
Data Rate
Signaling Level
AGP 3.0 1.5 V 3.3 V
PCI-66 Yes* Yes No
1x AGP No Yes No
2x AGP No Yes No
4x AGP Yes Yes No
8x AGP Yes No No