Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 151
System Address Map
4.1.6.1 AGP DRAM Graphics Aperture
The APBASE register follows the standard base address register template defined by the PCI 2.1
specification; however, the size of the range claimed by the APBASE register is programmed via
the APSIZE register. System BIOS programs this register before PCI Enumeration to be 4 MB,
8 MB, 16 MB, 32 MB, 64 MB, 128 MB or 256 MB. Once programmed, the APSIZE register forces
an appropriate number of the lower bits of the APBASE configuration register to read as 0 which in
turns limits the BAR size by hardware design. The default value of APSIZE forces a 256-MB
aperture. The aperture address range is aligned to a 4-MB boundary.
4.1.7 Device 2 Memory and Prefetchable Memory
Plug-and-play software configures the HI_B memory window to provide enough memory space
for the devices behind this PCI-to-PCI Bridge. Accesses that have addresses that fall within this
window are decoded and forwarded to HI_B for completion. The address ranges are:
• M2 MBASE2 to MLIMIT2
• PM2 PMBASE2 to PMLIMIT2
Note that these registers must be programmed with values that place the HI_B memory space
window between the value in the TOLM Register and 4 GB. In addition, neither region should
overlap with any other fixed or relocatable area of memory.
4.1.8 HI_A Subtractive Decode
All accesses that fall between the value programmed into the TOLM Register and 4 GB
(i.e., TOLM and 4 GB) are subtractively decoded and forwarded to HI_A if they do not decode to a
space that corresponds to another device.
4.2 I/O Address Space
The MCH does not support the existence of any other I/O devices on the system bus. The MCH
generates HI_A–B bus cycles for all processor I/O accesses. The MCH contains two internal
registers in the processor I/O space, Configuration Address Register (CONFIG_ADDRESS) and
the Configuration Data Register (CONFIG_DATA). These locations are used to implement the
configuration space access mechanism and are described in the Chapter 3.
The processor allows 64K+3 bytes to be addressed within the I/O space. The MCH propagates the
processor I/O address without any translation to the targeted destination bus. Note that the upper
three locations can be accessed only during I/O address wrap-around when signal A16# is asserted
on the system bus. A16# is asserted on the system bus whenever a DWord I/O access is made from
address 0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software attempts a two
bytes I/O access from address 0FFFFh.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
HI_A–B. All I/O cycles receive a Defer Response. The MCH never posts an I/O write.
The MCH never responds to I/O or configuration cycles initiated on any of the hub interfaces. Hub
interface transactions requiring completion are terminated with “master abort” completion packets
on the hub interfaces. Hub interface I/O write transactions not requiring completion are dropped.