Datasheet

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel
®
3210 MCH only)
254 Datasheet
8.52 VC0RCTL—VC0 Resource Control
B/D/F/Type: 0/6/0/MMR
Address Offset: 114–117h
Default Value: 800000FFh
Access: RO, RW
Size: 32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit Access
Default
Value
Description
31 RO 1b
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as VC0 can
never be disabled.
30:27 RO 0h Reserved
26:24 RO 000b
VC0 ID (VC0ID): This field assigns a VC ID to the VC resource. For VC0 this is
hardwired to 0 and read only.
23:20 RO 0000h Reserved
19:17 RW 000b
Port Arbitration Select: This field configures the VC resource to provide a
particular Port Arbitration service. This field is valid for RCRBs, Root Ports that
support peer to peer traffic, and Switch Ports, but not for PCI Express Endpoint
devices or Root Ports that do not support peer to peer traffic.
The permissible value of this field is a number corresponding to one of the
asserted bits in the Port Arbitration Capability field of the VC resource.
16:8 RO 00h Reserved
7:1 RW 7Fh
TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic Classes) that are
mapped to the VC resource. Bit locations within this field correspond to TC
values. For example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates that multiple
TCs are mapped to the VC resource. To remove one or more TCs from the TC/VC
Map of an enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
0RO1bTC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.