Datasheet

Introduction
18 Datasheet
DMI
Direct Media Interface is a proprietary chip-to-chip connection between the
MCH and ICH. This interface is based on the standard PCI Express*
specification.
Domain
A collection of physical, logical or virtual resources that are allocated to work
together. Domain is used as a generic term for virtual machines, partitions,
etc.
EP PCI Express Egress Port
FSB Front Side Bus. Synonymous with Host or processor bus
Full Reset
Full reset is when PWROK is de-asserted. Warm reset is when both RSTIN#
and PWROK are asserted.
MCH
Memory Controller Hub component that contains the processor interface,
DRAM controller, and PCI Express port. It communicates with the I/O
controller hub (Intel
®
ICH9) over the DMI interconnect. .
Host This term is used synonymously with processor
INTx An interrupt request signal where X stands for interrupts A, B, C and D
Intel
®
ICH9
Ninth generation I/O Controller Hub component that contains the primary PCI
interface, LPC interface, USB2.0, SATA, and other I/O functions. For this MCH,
the term ICH refers to the ICH9.
IOQ In Order Queue
MSI
Message Signaled Interrupt. A transaction conveying interrupt information to
the receiving agent through the same path that normally carries read and
write commands.
OOQ Out of Order Queueing
PCI Express*
A high-speed serial interface whose configuration is software compatible with
the legacy PCI specifications.
Primary PCI
The physical PCI bus that is driven directly by the Intel
®
ICH9.
Communication between Primary PCI and the MCH occurs over DMI. The
Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
Rank
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four
x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but
not always, mounted on a single side of a DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
SERR
System Error. An indication that an unrecoverable error has occurred on an
I/O bus.
SMI
System Management Interrupt. Used to indicate any of several system
conditions such as thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity.
Intel
®
TXT
Intel
®
Trusted Execution Technology (TXT) defines platform level
enhancements that provide the building blocks for creating trusted platforms.
VCO Voltage Controlled Oscillator
Term Description