Vol 2

Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family 5
Datasheet Volume Two: Functional Description, February 2014
7.4.10 Intel SMI2 Half-Width Failover Mode .........................................................56
7.4.11 Memory Migration ..................................................................................57
7.5 IIO RAS ...........................................................................................................57
7.5.1 IIO RAS Overview ..................................................................................57
7.5.2 IIO Module Error Reporting......................................................................57
7.5.3 PCI Express RAS .................................................................................... 58
7.6 System Level RAS Features ................................................................................59
8Reset Flow...............................................................................................................61
8.1 Introduction .....................................................................................................61
8.1.1 Cold Reset.............................................................................................61
8.1.2 Warm Reset ..........................................................................................61
9 Ubox Functional Description....................................................................................63
9.1 Ubox Overview .................................................................................................63
9.2 Interrupt and Event Delivery............................................................................... 63
9.3 Scratchpad Registers......................................................................................... 63
9.4 Sideband Interfaces...........................................................................................63
9.4.1 PECI Access...........................................................................................63
9.4.2 TAP Access............................................................................................64
10 PCU Functional Description......................................................................................65
10.1 Introduction .....................................................................................................65
10.2 Platform Environment Control Interface (PECI)......................................................66
10.2.1 PECI Client Capabilities ...........................................................................66
10.3 Platform Power Limits (RAPL)..............................................................................67
10.4 ACPI P-States...................................................................................................67
10.5 Turbo Modes.....................................................................................................67
10.6 DDR3 Power and Thermal Management................................................................68
10.6.1 DRAM Power Management.......................................................................68
10.6.2 DRAM Thermal Throttling ........................................................................68
10.7 Miscellaneous Functions .....................................................................................68
11 Performance Monitoring .......................................................................................... 69
11.1 Terminology .....................................................................................................69
11.2 Infrastructure...................................................................................................69
11.3 PCU PerfMon.....................................................................................................69
11.3.1 High-Level Overview...............................................................................69
12 Registers Overview and Configuration Process........................................................71
12.1 Platform Configuration Structure .........................................................................71
12.1.1 Processor IIO Devices (CPUBUSNO (0)).....................................................71
12.1.2 Processor Uncore Devices (CPUBUSNO (1))................................................73
12.2 Configuration Register Rules...............................................................................73
12.2.1 CSR Access ...........................................................................................74
12.2.2 MSR Access...........................................................................................79
12.2.3 Memory-Mapped I/O Registers.................................................................79
12.3 Register Terminology.........................................................................................79
12.4 Notational Conventions ......................................................................................81
12.4.1 Socket ID..............................................................................................81
12.4.2 Hexadecimal and Binary Numbers ............................................................81
13 Processor Uncore Configuration Registers...............................................................83
13.1 PCI Standard Registers ......................................................................................83
13.1.1 VID ......................................................................................................83
13.1.2 DID......................................................................................................84
13.1.3 PCICMD ................................................................................................84
13.1.4 PCISTS.................................................................................................85
13.1.5 RID ......................................................................................................86