Vol 1

Signal Descriptions
64 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
5.4 Intel QuickPath Interconnect Signals
5.5 PECI Signal
5.6 System Reference Clock Signals
5.7 JTAG and TAP Signals
Table 5-4. Intel QPI Port 0, 1 and 2 Signals
Signal Name Description
QPI{2:0}_CLKRX_DN/DP Reference Clock Differential Input. These pins provide the PLL
reference clock differential input. 100 MHz typ.
QPI{2:0}_CLKTX_DN/DP Reference Clock Differential Output. These pins provide the PLL
reference clock differential input. 100 MHz typ.
QPI{2:0}_DRX_DN/DP[19:00] Intel QPI Receive data input.
QPI{2:0}_DTX_DN/DP[19:00] Intel QPI Transmit data output.
Table 5-5. PECI Signals
Signal Name Description
PECI PECI (Platform Environment Control Interface) is the serial
sideband interface to the processor and is used primarily for
thermal, power and error management. Details regarding the PECI
electrical specifications, protocols and functions can be found in
the Platform Environment Control Interface Specification.
Table 5-6. System Reference Clock (BCLK{0/1}) Signals
Signal Name Description
BCLK{0/1}_D[N/P] Reference Clock Differential input. These pins provide the PLL
reference clock differential input into the processor. 100 MHz
typical BCLK0 is the Intel® QPI reference clock (system clock) and
BCLK1 is the PCI Express* reference clock.
Table 5-7. JTAG and TAP Signals (Sheet 1 of 2)
Signal Name Description
BPM_N[7:0] Breakpoint and Performance Monitor Signals: I/O signals from the
processor that indicate the status of breakpoints and
programmable counters used for monitoring processor
performance. These are 100 MHz signals.
EAR_N External Alignment of Reset, used to bring the processor up into a
deterministic state. This signal is pulled up on the die.
PRDY_N Probe Mode Ready is a processor output used by debug tools to
determine processor debug readiness.
PREQ_N Probe Mode Request is used by debug tools to request debug
operation of the processor.
TCK TCK (Test Clock) provides the clock input for the processor Test
Bus (also known as the Test Access Port).