Vol 1

Intel® Xeon® Product 2800/4800/8800 v2 Product Family 169
Datasheet Volume One, February 2014
PIROM
Note: Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not
rely on this model.
9.3.1 Header
To maintain backward compatibility, the Header defines the starting address for each
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
Example: Code looking for the processor uncore data of a processor would read offset
05h to find a value of 29. 29 is the first address within the 'Processor Uncore Data'
section of the PIROM.
9.3.1.1 DFR: Data Format Revision
This location identifies the data format revision of the PIROM data structure. Writes to
this register have no effect.
9.3.1.2 PISIZE: PIROM Size
This location identifies the PIROM size. Writes to this register have no effect.
9.3.1.3 PDA: Processor Data Address
This location provides the offset to the Processor Data Section. Writes to this register
have no effect.
Offset: 00h
Bit Description
7:0 Data Format Revision
The data format revision is used whenever fields within the PIROM are
redefined. The initial definition will begin at a value of 1. If a field, or bit
assignment within a field, is changed such that software needs to discern
between the old and new definition, then the data format revision field will be
incremented.
00h: Reserved
01h: Initial definition
02h: Second revision
03h: Third revision
04h: Fourth revision
05h:Fifth revision (Defined by this document)
06h-FFh: Reserved
Offset: 01h-02h
Bit Description
15:0 PIROM Size
The PIROM size provides the size of the device in hex bytes. The MSB is at
location 01h; the LSB is at location 02h.
0000h - 007Fh: Reserved
0080h: 128 byte PIROM size
0081- FFFFh: Reserved