Vol 1

Electrical Specifications
104 Intel® Xeon® Product 2800/4800/8800 v2 Product Family
Datasheet Volume One, February 2014
Notes:
1. Once up, VVMSE and VVMSE23, must stay up, even during memory hot plug.
2. Timing must be greater than 0ms.
3. VCCPECI is used by next generation CPUs. The pad is a no connect on package for Intel® Xeon® E7v2.
Can be supplied via local VTT (and VCCIO_IN) of each socket, in which case VCCPECI somes up with VTT.
Could also be supplied with Intel® C600 series chipset VPROC_IO (VCC_CPU_IO) at 1.0V, in which case
VCCPECI comes up much earlier than VVMSE. Both usage cases are valid.
4. All sockets within a node, sharing common signals power up VTT together. Shared common CPU signals are
pulled up by one VTT VR.
5. Memory can power on with the system, or when enabled by BIOS. When powered on with the system,
there is no specific VVMSE ordering (unless shared with CPU and VR). Turn on the memory power before
CPU PWRGOOD to allow SVID loads to power up before the CPU drives SVID. Also recommend power on
Intel® C102/C104 Scalable Memory Buffer’s Vcore with CPU VTT.
6. Timing must be equal to or greater than 1ms
7. Must be pulled up to VTT. Reflects the status of VTT and VMSE.
8. PWRGOOD_VMSE required to rise and be stable prior to rise of VSA. For next generation CPUs, VSA will
never ramp. VSA required to rise and be stable prior to rise of VCCPLL. Values are per VR 12.5.
9. VSA required to rise and be stable prior to rise of VCCPLL. Values are per VR 12.5. For follow on CPUs
VCCPLL will never ramp.
10. For BCLK, PWRGOOD, EAR_N, or PWR_DEBUG_N, delays from any driver to that pin on each socket in a
system must be within 1 base clock cycle. BCLK pair wire latency between sockets must be within 1/2 base
clock cycle.
Figure 6-22. Voltage Sequence Timing Requirements