Hub Datasheet

88 Intel
®
E7505 Chipset MCH Datasheet
Register Description
3.6.17 SMICMD_HIA—SMI Command Register (D0:F1)
Address Offset: 5Ah
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determine whether SMI will be generated when the associated flag is set in either the
HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or HIA_NERR
Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD, SMICMD, or
SCICMD Registers, respectively. Only one message type can be enabled.
3.6.18 SERRCMD_HIA—SERR Command Register (D0:F1)
Address Offset: 5Ch
Default Value: 00h
Sticky No
Attribute: RO, R/W
Size: 8 bits
This register determine whether SERR will be generated when the associated flag is set in either
the HIA_FERR or HIA_NERR Register. When an error flag is set in the HIA_FERR or
HIA_NERR Register, it can generate an SERR, SMI, or SCI when enabled in the SERRCMD,
SMICMD, or SCICMD Registers, respectively. Only one message type can be enabled.
Bits
Default,
Access
Description
7 Reserved
6
0b
R/W
SMI on HI_A Target Abort Enable.
0 = No SMI generation
1 = Generate SMI if bit 6 is set in HIA_FERR or HIA_NERR
5 Reserved
4
0b
R/W
SMI on HI_A Data Parity Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 4 is set in HIA_FERR or HIA_NERR
3:1 Reserved
0
0b
R/W
SMI on HI_A Data Address/Comment Error Detected Enable.
0 = No SMI generation
1 = Generate SMI if bit 0 is set in HIA_FERR or HIA_NERR
Bits
Default,
Access
Description
7 Reserved
6
0b
R/W
SERR on HI_A Target Abort Enable.
0 = No SERR generation
1 = Generate SERR if bit 6 is set in HIA_FERR or HIA_NERR
5 Reserved
4
0b
R/W
SERR on HI_A Data Parity Error Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 4 is set in HIA_FERR or HIA_NERR
3:1 Reserved
0
0b
R/W
SEER on HI_A Data Address/Comment Error Detected Enable.
0 = No SERR generation
1 = Generate SERR if bit 0 is set in HIA_FERR or HIA_NERR