Hub Datasheet

Intel
®
E7505 Chipset MCH Datasheet 67
Register Description
3.5.23 DDR_CNTL—DDR Memory Control Register (D0:F0)
Address Offset: 8Eh
Default Value: 00xx 0000b
Attribute: RO, R/W
Size: 8 bits
Bits
Default,
Access
Description
7
0b
R/W
DDR Refresh Frequency. This bit is set by the BIOS to the DDR refresh frequency. It is
used by the refresh timer to set the refresh period properly according to the number of
clocks per microsecond. This is an indicator bit to the DDR logic only. It does not
change the DDR frequency.
0 = 100 MHz (200 MHz data rate)
1 = 133 MHz (266 MHz data rate).
6:5 Reserved
4
x
RO
DRAM Strap, latched. This bit provides the value of the DRAM strap pin, latched at
reset. It is used to determine the motherboard type.
0 = Registered only motherboard
1 = Unbuffered DIMM support.
3 Reserved
2
0b
R/W
CS# / Clock Muxing. This bit determines whether the multiplexed DRAM pins are used
as clocks or chip selects. See the pin description for the specific muxing.
0 = CS_x[5:4] are output on the multiplexed pins. Used on third DIMM slot on registered
(only) mother board.
1:0 Reserved