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54 Intel

E7505 Chipset MCH Datasheet

3.5.15 MCHCFG—MCH Configuration Register (D0:F0)

Address Offset: 50–51h

Default Value: 0004h

Attribute: RO, R/W

Size: 16 bits

Bits

Default,

Access

Description

15 Reserved

14:13

00b

R/W

Number of Stop Grant Cycles (NSG). This field contains the number of Stop Grant

transactions expected on the SB bus before a Stop Grant Acknowledge packet is sent

to the Intel

ICH4. This field is programmed by the BIOS after it has enumerated the

processors and before it has enabled Stop Clock generation in the ICH4. Once this

field has been set, it should not be modified. Note that each enabled thread within

each processor will generate Stop Grant Acknowledge transactions.

Note that this register is read/write and not Write-once as in some implementations.

00 = HI_A Stop Grant generated after 1 System Bus Stop Grant

01 = HI_A Stop Grant generated after 2 System Bus Stop Grant

10 = HI_A Stop Grant generated after 3 System Bus Stop Grant

11 = HI_A Stop Grant generated after 4 System Bus Stop Grant

12:10 Reserved

R/W

Aperture Access Global Enable (APEN). This bit is used to prevent access to the

graphics aperture from any port (processor, HI_A, HI_B, or, AGP) before the aperture

range is established by the configuration software and appropriate translation table in

the main memory has been initialized. Since the default value is 0, this field must be

set after the system is fully configured to enable aperture accesses. Set by Drivers.

8:6 Reserved

R/W

MDA Present (MDAP). This bit works with the VGA enable bits in the BCTRL registers

of devices 2–4 to control the routing of processor-initiated transactions targeting MDA

compatible I/O and memory address ranges. This bit should not be set if none of the

VGA enable bits are set. If none of the VGA enable bits are set, then accesses to I/O

address range x3BCh–x3BFh are forwarded to HI_A. If the VGA enable bit is not set,

then accesses to I/O address range x3BCh–x3BFh are treated just like any other I/O

accesses. That is, the cycles are forwarded to HI_B if the address is within the

corresponding IOBASE and IOLIMIT and ISA enable bit is not set; otherwise, they are

forwarded to HI_A. MDA resources are defined as the following:

Memory: 0B0000h–0B7FFFh

I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,

(including ISA address aliases, A15:10 are not used in decode)

Any I/O reference that includes the I/O locations listed above, or their aliases, will be

forwarded to hub interface even if the reference includes I/O locations not listed above.

The following table shows the behavior for all combinations of MDA and VGA:

VGA MDA Behavior

0 1 All References to MDA and VGA go to HI_A

0 1 Illegal Combination (DO NOT USE)

1 0 All References to VGA go to device with VGA enable set. MDA-only

references (I/O address 3BF and aliases) will go to HI_A.

1 1 VGA References go to the HI which has its BCTRL3 bit set; MDA

references go to HI_A