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Intel
®
E7505 Chipset MCH Datasheet 165
Functional Description
5.5 Main Memory Interface
The memory interface supports a dual channel DDR system memory with registered or unbuffered
SDRAM DIMMs. The MCH only supports DDR-SDRAM type of memory. The MCH does not
support SDR SDRAM (PC-100/133) type of memory. Table 5-6 defines the some of the terms used
in this section
Table 5-6. DRAM Terminology
Term Definition
DDR
Double Data Rate. This term describes the type of DRAMs that transfer two data items
per clock on each pin. This is the only type of DRAM supported by the MCH.
DIMM
Dual Inline Memory Module. A PC board containing 4 to 36 DRAM chips that the end
user can install into the DIMM sockets on the motherboard.
Single-Sided DIMM
Single-Sided DIMM usually describes a DIMM that contains one DRAM row. Usually,
one row fits on a single side of the DIMM allowing the backside to be empty; when
using x4 DRAM chips, both sides are required for a single row. This terminology is not
used within this document.
Double-Sided DIMM
Double-Sided DIMM usually describes a DIMM that contains two DRAM rows.
Generally, a Double-Sided DIMM contains two rows, with the exception noted above.
This terminology is not used within this document.
Stacked DIMM
Stacked DIMM describes a dual row DIMM using x4 DRAM parts. The x4 parts require
18 chips for each row or 36 chips for two rows. A DIMM generally only has room for 18
DRAM chips; thus, the two DRAM rows are stacked on top of each other with specially
pined out DRAMs such that the CS and CKE pins for the bottom row are on different
pins than the CS and CKE pins for the top row. These DIMMs are used in workstations
to maximize DRAM capacity.
They are only available on registered DIMMs.
Registered DIMM
In a registered DIMM the address and control signals are buffered through a flip-flop
(register) and the clock is buffered by a PLL circuit. A registered DIMM presents only
one load on the clock, address, and command lines, but delays the address and
command by one clock. There is no register on the data pins. These DIMMs are often
used on workstations to achieve a higher memory capacity. They can carry a significant
cost premium.
Unbuffered DIMM
In an unbuffered DIMM the clocks, address, and control signals of each DRAM chip are
driven by the DRAM controller with no buffer or register. These are the standard DIMMs
used on most desktop systems and many low end workstation and servers.
Buffered DIMM
(not used)
There are no DIMMs with just a buffer that is not a flip-flop. This term should not be
used.
Unregistered DIMM
(not used)
The term “Unbuffered” should be used instead of Unregistered.
SPD
Serial Presence Detect. This is a serial EE ROM on all DIMMs that contain data such
as the number of rows, DRAM type (technology, chip width, page size, timing
parameters, etc.), manufacturer, and other information. This information is read by the
BIOS via the SMBus controller on the ICH to determine what memory is installed in the
system.
Row
A group of DRAM chips that fill out the data bus width of the system and are accessed
in parallel by each DRAM command.Tthe MCH data width is 144 bits. A DIMM pair may
contain either 1 or 2 rows.
Bank
DRAM chips are divided into multiple banks internally. Commodity parts are 4 bank,
which is the only type the MCH supports. Each bank acts somewhat like a separate
DRAM; opening and closing pages independently and allowing different pages to be
open in each. Most commands to a DRAM target a specific bank; however, some
commands (i.e., Precharge All) are targeted at all banks. Multiple banks allows higher
performance by interleaving the banks and reducing page miss cycles.