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148 Intel
®
E7505 Chipset MCH Datasheet
System Address Map
4.1.1 VGA and MDA Memory Spaces
Video cards use these legacy address ranges to map a frame buffer or a character-based video
buffer. The address ranges in this memory space are:
• VGAA 0_000A_0000h to 0_000A_FFFFh
• MDA 0_000B_0000h to 0_000B_7FFFh
• VGAB 0_000B_8000h to 0_000B_FFFFh
By default, accesses to these ranges are forwarded to HI_A. However, if the VGA_EN bit is set in
the BCTRL configuration register, then transactions within the VGA and MDA spaces are sent to
AGP or HI_B, respectively.
Note: The VGA_EN bit may be set in one and only one of the BCTRL Registers. Software must not set
more than one of the VGA_EN bits.
If the configuration bit MCHCFG. MDAP is set, then accesses that fall within the MDA range will
be sent to HI_A without regard for the VGAEN bits. Legacy support requires the ability to have a
second graphics controller (monochrome) in the system. In a MCH based-system, accesses in the
standard VGA range are forwarded to AGP or HI_B (depending on configuration bits). Since the
monochrome adapter may be on the HI_A/PCI (or ISA) bus, the MCH must decode cycles in the
MDA range and forward them to HI_A. This capability is controlled by a configuration bit (MDAP
bit). In addition to the memory range B0000h to B7FFFh, the MCH decodes I/O cycles at 3B4h,
3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to HI_A.
An optimization allows the system to reclaim the memory displaced by these regions. If SMM
memory space is enabled by SMRAM.G_SMRARE and either the SMRAM.D_OPEN bit is set or
the processor bus receives an SMM-encoded request for code (not data), then the transaction is
steered to system memory rather than HI_A. Under these conditions, both the VGAEN bits and the
MDAP bit are ignored.
If any VGAEN is set, then all ISAEN must be set. The PCI specification defines VGAEN to be a
10-bit decode. Therefore, the other peer bridges must also be 10-bit decodes (ISAEN), so that two
or more devices do not claim the same access.