Hub Datasheet
Intel
®
E7505 Chipset MCH Datasheet 139
Register Description
3.9.11 HIB_FERR—HI_B First Error Register (D2:F1)
Address Offset: 80h
Default Value: 00h
Sticky Yes
Attribute: R/WC
Size: 8 bits
This register store the FIRST error related to the HI_B interface. Only one error bit will be set in
this register. Any future errors (NEXT Errors) will be set in the HIB_NERR register. No further
error bits in this register will be set until the existing error bit is cleared.
Note: Software must write a 1 to clear bits that are set.
Bits
Default,
Access
Description
7 Reserved
6
0b
R/WC
MCH Received SERR From HI_B.
0 = No SERR from HI_B detected.
1 = MCH detected a SERR on Hub Interface_B.
5
0b
R/WC
MCH Master Abort on HI_B (HIBMA). MCH did a master abort to a HI_B request.
0 = No Master Abort on HI_B detected.
1 = MCH detected an invalid address that will be master aborted. This bit is set even
when the MCH does not respond with the Master Abort completion packet.
4
0b
R/WC
Received Target Abort on HI_B.
0 = No Target Abort on HI_B detected.
1 = MCH detected that an MCH originated cycle was terminated with a Target Abort
completion packet.
3
0b
R/WC
Correctable Error on Header/Address from HI_B.
0 = No correctable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a single bit correctable error.
2
0b
R/WC
Correctable Error on Data from HI_B.
0 = No correctable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a single bit correctable error.
1
0b
R/WC
Uncorrectable Error on Header/Address from HI_B.
0 = No uncorrectable error on header/address from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a multi-bit uncorrectable error.
0
0b
R/WC
Uncorrectable Error on Data Transfer from HI_B.
0 = No uncorrectable error on data from HI_B detected.
1 = Even when error correction is turned off, this bit may be set if a packet is received
that has a multi-bit uncorrectable error.