Datasheet

Datasheet 9
8.52 VC0RCTL—VC0 Resource Control....................................................................... 254
8.53 VC0RSTS—VC0 Resource Status........................................................................ 255
8.54 RCLDECH—Root Complex Link Declaration Enhanced............................................ 255
8.55 ESD—Element Self Description.......................................................................... 256
8.56 LE1D—Link Entry 1 Description ......................................................................... 257
8.57 LE1A—Link Entry 1 Address.............................................................................. 257
9 Direct Media Interface (DMI) RCRB ....................................................................... 259
9.1 DMIVCECH—DMI Virtual Channel Enhanced Capability.......................................... 260
9.2 DMIPVCCAP1—DMI Port VC Capability Register 1................................................. 260
9.3 DMIPVCCTL—DMI Port VC Control...................................................................... 261
9.4 DMIVC0RCAP—DMI VC0 Resource Capability....................................................... 261
9.5 DMIVC0RCTL0—DMI VC0 Resource Control......................................................... 262
9.6 DMIVC0RSTS—DMI VC0 Resource Status............................................................ 263
9.7 DMIVC1RCAP—DMI VC1 Resource Capability....................................................... 263
9.8 DMIVC1RCTL1—DMI VC1 Resource Control......................................................... 264
9.9 DMIVC1RSTS—DMI VC1 Resource Status............................................................ 265
9.10 DMILCAP—DMI Link Capabilities........................................................................ 265
9.11 DMILCTL—DMI Link Control.............................................................................. 266
9.12 DMILSTS—DMI Link Status............................................................................... 266
10 Functional Description........................................................................................... 267
10.1 Host Interface................................................................................................. 267
10.1.1 FSB IOQ Depth .................................................................................... 267
10.1.2 FSB OOQ Depth ................................................................................... 267
10.1.3 FSB GTL+ Termination.......................................................................... 267
10.1.4 FSB Dynamic Bus Inversion ................................................................... 267
10.1.5 APIC Cluster Mode Support.................................................................... 268
10.2 System Memory Controller ............................................................................... 269
10.2.1 System Memory Organization Modes....................................................... 269
10.2.1.1 Single Channel Mode............................................................... 269
10.2.1.2 Dual Channel Modes................................................................ 269
10.2.2 System Memory Technology Supported................................................... 270
10.2.3 Error Checking and Correction................................................................ 271
10.3 PCI Express* .................................................................................................. 274
10.3.1 PCI Express* Architecture ..................................................................... 274
10.3.1.1 Transaction Layer ................................................................... 274
10.3.1.2 Data Link Layer ...................................................................... 274
10.3.1.3 Physical Layer ........................................................................ 274
10.4 Thermal Sensor............................................................................................... 275
10.4.1 PCI Device 0, Function 0 ....................................................................... 275
10.4.2 MCHBAR Thermal Sensor Registers......................................................... 275
10.5 Power Management ......................................................................................... 276
10.6 Clocking......................................................................................................... 276
11 Electrical Characteristics ....................................................................................... 279
11.1 Absolute Minimum and Maximum Ratings ........................................................... 279
11.2 Current Consumption....................................................................................... 281
11.3 Signal Groups................................................................................................. 282
11.4 Buffer Supply and DC Characteristics ................................................................. 285
11.4.1 I/O Buffer Supply Voltages .................................................................... 285
11.4.2 General DC Characteristics .................................................................... 286
12 Ballout and Package Information........................................................................... 289
12.1 Ballout Information.......................................................................................... 289
12.2 Package Information........................................................................................ 313