Datasheet

Datasheet 125
DRAM Controller Registers (D0:F0)
5.2.36 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: A0A–A0Bh
Default Value: 0000h
Access: RW
Size: 16 bits
See C0DRA01 register.
5.2.37 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: A19–A1Ah
Default Value: 0000h
Access: RW, RO
Size: 16 bits
EPD CYCTRK WRT PRE Status registers.
Bit Access
Default
Value
Description
15:8 RW 00h
Channel 0 DRAM Rank-3 Attributes (C0DRA3): This register defines DRAM
pagesize/number-of-banks for rank3 for given channel.
7:0 RW 00h
Channel 0 DRAM Rank-2 Attributes (C0DRA2): This register defines DRAM
pagesize/number-of-banks for rank2 for given channel.
Bit Access
Default
Value
Description
15:11 RW 00000b
ACTTo PRE Delayed (C0sd_cr_act_pchg): This field indicates the minimum
allowed spacing (in DRAM clocks) between the ACT and PRE commands to the
same rank-bank
10:6 RW 00000b
Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the minimum
allowed spacing (in DRAM clocks) between the WRITE and PRE commands to the
same rank-bank
5:2 RW 0000b
READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and PRE commands to the
same rank-bank
1:0 RO 00b Reserved